Semiconductor memory device and data write and read methods thereof

ABSTRACT

A semiconductor memory device having a first memory cell array block including a memory cell having a floating body, the memory cell coupled to a word line, a first bit line, and a first source line, a second memory cell array block including a reference memory cell having a floating body, the reference memory cell coupled to a reference word line, a second bit line, and a second source line, a first isolation gate portion configured to selectively transmit a signal between the first bit line and at least one of a sense bit line and an inverted sense bit line, a second isolation gate portion configured to selectively transmit a signal between the second bit line and at least one of the sense bit lines, and a sense amplifier configured to amplify voltages of the sense bit line and the inverted sense bit line to first and second sense amplifying voltage levels.

This application is a Divisional of application Ser. No. 11/560,223,filed Nov. 15, 2006, which claims the benefit of Korean PatentApplication No. 2006-14852, filed Feb. 15, 2006, the contents of whichare hereby incorporated herein by reference in their entirety.

BACKGROUND

1. Technical Field

This disclosure relates to a semiconductor memory device, and moreparticularly, to a semiconductor memory device including a dynamicmemory cell composed of a transistor with a floating body, and datawrite and read methods thereof.

2. Description of Related Art

A typical dynamic memory cell includes one access transistor and onedata storage capacitor. When the data storage capacitor is charged, data“1” is stored; while when no charge is charged in the data storagecapacitor, data “0” is stored. However, since the charge in the datastorage capacitor is lost after a predetermined time elapses, a refresh(restore) operation should be performed.

In addition, since the typical dynamic memory cell needs the capacitor,when a memory cell array is includes the typical dynamic memory cells,layout area must be used for capacitors, thus there is a limit to howmuch the layout area of a semiconductor memory device may be reduced.

For this reason, a transistor having a floating body has been proposed.In this transistor, the floating body, which stores majority carriers,may need to be refreshed because the stored majority carriers are lostafter a predetermined time elapses. Thus, although a memory cellincluding a transistor with a floating body does not include a capacitorunlike a typical memory cell, the memory cell including the transistorwith the floating body operates similarly to the capacitor so that itcan be used as a dynamic memory cell.

In other words, the transistor having the floating body constitutes onememory cell. Thus, assuming that a semiconductor memory device with aparticular capacity is fabricated using memory cells with a transistorhaving a floating body, the semiconductor memory device including memorycells with transistor having a floating body has a smaller layout areathan that of a semiconductor memory device including a typical memorycell.

FIG. 1 illustrates a conventional semiconductor memory device includinga memory cell with a floating body. The semiconductor memory deviceincludes memory cell array blocks BLK1 and BLK2, bit line selectors10-11 to 10-1 m and 10-21 to 10-2 m, a reference bit line selector 12-1,level limiters 14-1 to 14-m, 14-(m+1), sense amplifiers 16-1 to 16-m, areference voltage generator 18, comparators COM1 to COMm, latches LA1 toLAm, write back gates WBG1 to WBGm, read column selection gates RG1 toRBm, write column selection gates WG1 to WGm, and a reference writecolumn selection gate RWG.

Each of the memory cell array blocks BLK1 and BLK2 includes memory cellsMC and reference memory cells RMC. During a write operation, when apredetermined voltage (e.g., 1.5 V) is applied to the corresponding wordline and a voltage higher than the predetermined voltage (e.g., over 1.5V) is applied to the corresponding bit line, a lot of electron-holepairs are generated due to impact ionization near the drain of an NMOStransistor of the corresponding memory cell MC. Here, electrons areabsorbed in the drain of the NMOS transistor and holes are stored in afloating body, so that data “1” is written. That is, when the data “1”is written, the NMOS transistor operates in a saturation region. On theother hand, when a predetermined voltage (e.g., 1.5 V) is applied to thecorresponding word line and a voltage (e.g., −1.5 V) lower than thepredetermined voltage is applied to the corresponding bit line, thefloating body and the drain of the NMOS transistor are forward-biased,so that the holes stored in the floating body are mostly discharged tothe drain. As a result, data “0” is written.

When the data “1” is stored, the threshold voltage of the NMOStransistor decreases, and when the data “0” is stored, the thresholdvoltage of the NMOS transistor increases. In addition, during a readoperation, when a predetermined voltage (e.g., 1.5 V) is applied to thecorresponding word line and a voltage for operating of the NMOStransistor in a linear region (e.g., 0.2 V) is applied to thecorresponding bit line, a current difference occurs in the correspondingbit line. By sensing the current difference, the memory cell reads data“0” and data “1.” When the memory cell stores data “1,” a bit linecurrent generated when the data “1” is read increases due to a lowthreshold voltage. By comparison, when the memory cell stores data “0,”a bit line current generated when the data “0” is read decreases due toa high threshold voltage.

Each of the bit line selectors 10-11 to 10-1 m and 10-21 to 10-2 mselects one of the k bit lines BL1 to BLk of each of sub memory cellarray blocks SBLK11 to SBLK1 m and SBLK21 to SBLK2 m in response to eachof bit line selection signals BS1 to BSk and couples the selected bitline with the corresponding one of sense bit lines SBL1 to SBLm. Each ofthe reference bit line selectors 12-1 and 12-2 connects reference bitlines RBL1 and RBL2 of each of reference memory cell array blocks RBLK1and RBLK2 with a reference sense bit line RSBL in response to thecorresponding one of reference bit line selection signals RBS1 and RBS2.

Each of the level limiters 14-1 to 14-m, and 14-(m+1) cuts off thesupply of the corresponding one of currents Ic1 to Ic(m+1) to thecorresponding one of the sense bit lines SBL1 to SBLm and the referencesense bit line RSBL when the corresponding one of the sense bit linesSBL1 to SBLm and the reference sense bit line RSBL is at a highervoltage level than a limited voltage VBLR. That is, when the level ofthe limited voltage VBLR is set to 0.2 V, a voltage for a read operationis applied to the bit lines BL1 to BLk and the reference bit lines RBL1and RBL2 due to the level limiters 14-1 to 14-(m+1) so as to allow theflow of the corresponding one of the currents Ic1 to Ic(m+1). Here, thereason that the limited voltage VBLR is set to a low level of 0.2 V isthat when the limited voltage VBLR is set to a higher level than 0.2 V,the NMOS transistor with the floating body is biased in a saturatedstate so that when data “0” is read, data “1” may be read incorrectlydue to impact ionization. The reference voltage generator 18 generates areference voltage VREF corresponding to the current Ic(m+1). Each of thesense amplifiers 16-1 to 16-m senses the corresponding one of thecurrents Ic1 to Icm and generates a voltage corresponding to the sensedcurrent. The reference voltage VREF generated by the reference voltagegenerator 18 is between voltages corresponding to the data “0” and thedata “1,” which are output from each of the sense amplifiers 16-1 to16-m.

The write and read operations of the semiconductor memory device shownin FIG. 1 will now be described.

First, the write operation of the reference memory cells RMC will bedescribed.

When a voltage of 1.5 V is applied to the word line WL11 and thereference bit line selection signal RBS1 is activated, the reference bitline RBL1 is coupled to the reference sense bit line RSBL. When areference write column selection signal RWCSL is activated, an NMOStransistor N7 is turned on, and thus data transmitted to a write dataline WD is transmitted through the reference sense bit line RSBL to thereference bit line RBL1. In this case, when write data has a voltage of−1.5 V, data “0” is written in the reference memory cell RMC connectedbetween the word line WL11 and the reference bit line RBL1. In the samemanner, the data “0” is written in all the reference memory cells RMCconnected between other word lines and the reference bit lines RBL1. Inaddition, data “1” is written in all the reference memory cells RMCconnected between the word lines WL11 to WL1 n and WL21 to WL2 n and thereference bit lines RBL2. In this case, write data may have a voltage of1.5 V.

In other words, data “0” is written in the reference memory cells RMCconnected to the reference bit lines RBL1 of the respective referencememory cell array blocks RBLK1 and RBLK2, and data “1” is written in thereference memory cells RMC connected to the reference bit lines RBL2thereof. Thus, the reference memory cells RMC to the reference bit linesRBL1 and RBL2 of the respective reference memory cell array blocks RBLK1and RBLK2 are used to generate the reference voltage VREF during theread operation.

Next, the write operation of the memory cell MC will be described. Whena voltage of 1.5 V is applied to the word line WL 1I and the bit lineselection signal BS I is activated, the bit line BL1 is connected to thesense bit line SBL1. When a write column selection signal WCSL1 isactivated, an NMOS transistor N6 is turned on. In this case, when avoltage of −1.5 V is applied to the write data line WD, the voltage isapplied through the sense bit line SBL1 to the bit line BL1 so that data“0” is written in the memory cell MC connected between the word lineWL11 and the bit line BL1. On the other hand, when a voltage of 1.5 V isapplied to the write data line WD, data “1” is written. In the samemanner, all the memory cells MC perform the write operation.

The read operation of the memory cells MC will now be described. When avoltage of 1.5 V is applied to the word line WL11 and the bit lineselection signal BS1 is activated, the bit line BL1 is connected to thesense bit line SBL1 so that a signal is transmitted from the bit lineBL1 to the sense bit line SBL1. In this case, the reference bit lineselection signals RBS1 and RBS2 are activated at the same time, and thusthe reference bit lines RBL1 and RBL2 are connected to the referencesense bit line RSBL, and a signal is transmitted from the reference bitlines RBL1 and RBL2 to the reference sense bit line RSBL.

The level limiter 14-1 prevents the supply of current from an outputnode of the level limiter 14-1 to the sense bit line SBL1 when the sensebit line SBL1 is at a higher voltage level than the limited voltageVBLR, so that the sense bit line SBL1 remains at a lower voltage levelthan the limited voltage VBLR. Also, the level limiter 14-1 generatesthe current Ic 1 corresponding to data stored in the memory cell MC. Thelevel limiter 14-(m+1) prevents the supply of current from an outputnode of the level limiter 14-(m+1) to the reference sense bit line RSBLwhen the reference sense bit line RSBL is at a higher voltage level thanthe limited voltage VBLR, so that the reference sense bit line RSBLremains at a lower voltage level than the limited voltage VBLR. Also,the level limiter 14-(m+1) generates the current Ic(m+1) correspondingdata stored in the reference memory cell RMC.

The sense amplifier 16-1 senses the current Ic1 and generates a sensingvoltage sn1. The reference voltage generator 18 senses the currentIc(m+1) and generates a reference voltage VREF. The comparator COM1 isenabled in response to the sense amplifier enable signal SEN, comparesthe sensing voltage sn1 generated by the sense amplifier 16-1 with thereference voltage VREF, and generates sensing data. That is, when thesensing voltage sn1 generated by the sense amplifier 16-1 is lower thanthe reference voltage VRLF, the comparator COM1 outputs a high-levelsignal to the corresponding node “a.” Inversely, when the sensingvoltage sn1 is higher than the reference voltage VREF, the comparatorCOM1 outputs a low-level signal to the corresponding node “a.” The latchLA1 latches the sensing data.

In addition, when a read column selection signal RCSL1 is activated,NMOS transistors N2 and N4 are turned on. In this case, when the node“a” is at a high level, an NMOS transistor N5 is turned on and transmitslow-level data to an inverted read data line RDB. On the other hand,when a node “b” is at a high level, an NMOS transistor N3 is turned onand transmits the low-level data to a read data line RD. That is, thelow-level data is transmitted to the read data line RD or the invertedread data line RDB during the read operation.

After the read operation, when the write back signal WB is activated, anNMOS transistor NI is turned on, so that high-level data is transmittedfrom the sense bit line SBL1 to the bit line BL1. Thus, a refreshoperation is performed on the memory cell MC that stores data “1” and isconnected between the word line WL11 and the bit line BL1. In the samemanner, all the memory cells MC perform the read operation.

Thus, in order to perform a read operation, a conventional semiconductormemory device including memory cells with a floating body, a complicatedcircuit configuration including level limiters, sense amplifiers,comparators, latches, and write back gates as shown in FIG. 1 is needed.

Also, for the conventional semiconductor memory device, a long period oftime is needed to perform a refresh operation. This is because a circuitconfiguration connected between a pair of sense bit lines, which is usedfor a read operation (or a refresh operation), is shared by k pairs ofbit lines. In other words, one word line needs to be activated k timesso that all the memory cells can perform the refresh operation.

SUMMARY OF THE INVENTION

An embodiment includes a semiconductor memory device having a firstmemory cell array block including a memory cell having a floating body,the memory cell coupled to a word line, a first bit line, and a firstsource line, a second memory cell array block including a referencememory cell having a floating body, the reference memory cell coupled toa reference word line, a second bit line, and a second source line, afirst isolation gate portion configured to selectively transmit a signalbetween the first bit line and at least one of a sense bit line and aninverted sense bit line, a second isolation gate portion configured toselectively transmit a signal between the second bit line and at leastone of the sense bit lines and the inverted sense bit line, and a senseamplifier configured to amplify voltages of the sense bit line and theinverted sense bit line to first and second sense amplifying voltagelevels.

Another embodiment includes a semiconductor device including memory cellarray blocks, each memory cell block including bit lines, word lines, areference word line, memory cells having floating bodies where each bitline is coupled to a corresponding subset of the memory cells, andreference memory cells having floating bodies and coupled to thereference word line where each bit line also coupled to a correspondingreference memory cell. In addition, the semiconductor device includesisolation gates with each isolation gate coupled to the bit lines of acorresponding memory cell array block, and sense amplifiers coupled tothe isolation gates.

Another embodiment includes a method of operating a semiconductor memorydevice including memory cells having floating bodies. The methodincludes activating a word line of a first memory cell array, activatinga reference word line of a second memory cell array, coupling a bit lineof the first memory cell array to a sense bit line of a sense amplifier,coupling a bit line of the second memory cell array to an inverted sensebit line of the sense amplifier, and amplifying a difference between thesense bit line and the inverted sense bit line.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other objects, features and advantages will becomeapparent from the following detailed description of embodiments inreference to the accompanying drawings. The drawings may not necessarilybe to scale, emphasis instead being placed upon illustrating theembodiments.

FIG. 1 illustrates a conventional semiconductor memory device includinga memory cell with a floating body.

FIG. 2 is a block diagram of a semiconductor memory device according toan embodiment.

FIG. 3 is a timing diagram illustrating a reference write operation ofthe semiconductor memory device shown in FIG. 2.

FIG. 4 is a timing diagram illustrating a write operation of thesemiconductor memory device shown in FIG. 2.

FIG. 5 is a timing diagram illustrating a read operation of thesemiconductor memory device shown in FIG. 2.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of a semiconductor memory device and data write and readmethods thereof will now be described more fully hereinafter withreference to the accompanying drawings.

FIG. 2 is a block diagram of a semiconductor memory device according toan embodiment. The semiconductor memory device includes a memory cellarray 100, a row decoder 110, a column decoder 120, and a controller130, and the memory cell array 100 includes memory cell array blocksBLK0 to BLK(k+1), isolation gates ISO to IS(k+1), precharge circuitsPRE, sense amplifiers PSA and NSA, and column selection gates CSG.

In FIG. 2, each block “SA” denotes a sense amplifier circuit includingthe precharge circuit PRE, the bit line sense amplifier PSA and NSA, andthe column selection gate CSG.

The precharge circuit PRE includes NMOS transistors N1 and N2. The senseamplifier includes a PMOS sense amplifier PSA and an NMOS senseamplifier NSA. The PMOS sense amplifier PSA includes PMOS transistors P1and P2. The NMOS sense amplifier NSA includes NMOS transistors N3 andN4. The column selection gate CSG includes NMOS transistors N5 and N6.Each of the isolation gates IS1 to ISk includes NMOS transistors N7 andN8.

The semiconductor memory device shown in FIG. 2 is configured such thattwo pairs of data may be input and output through two pairs of datalines disposed on both sides of the memory cell array blocks BLK1 toBLKk.

In FIG. 2, each of the memory cell array blocks BLK1 to BLKk includesreference NMOS transistors RM and NMOS transistors M. Each referenceNMOS transistor has a floating body and a gate coupled to a referenceword line RWL, a drain coupled to one of bit lines BL1, BL2, . . . , anda source coupled in common to a common source line. Each NMOS transistorM has a floating body and a gate coupled to one of word lines WL11 toWL1n, a drain coupled to one of bit lines BL1, BL2, . . . , and a sourcecoupled in common to the common source line.

Each of the memory cell array blocks BLK0 and BLK(k+1) includesreference NMOS transistors RM. Each reference NMOS transistor having afloating body and a gate coupled to reference word lines RWL0 andRWL(k+1), a drain coupled to the bit lines BL1, BL2, . . . , a sourcecoupled in common to the common source line. The reference NMOStransistors RM constitute reference memory cells, and the NMOStransistors M constitute memory cells. Also, the common source line iscoupled in common to a voltage such as a ground voltage.

Although with reference to FIG. 2 the memory cell array blocks BLK0 andBLK(k+1) are described above as configured differently from the memorycell array blocks BLK1 to BLKk, the memory cell array blocks BLK0 andBLK(k+1) may have the same configuration as the memory cell array blocksBLK1 to BLKk.

Functions of the respective blocks shown in FIG. 2 will now bedescribed.

In each of the memory cells M of the memory cell array blocks BLK1 toBLKk, during a write operation, when a predetermined voltage (e.g., 1.6V) is applied to the corresponding one of word lines WL11 to WLkn and ahigher voltage (e.g., 2.3 V) is applied to the corresponding one of thebit lines BL1, BL2, . . . , data “0” is written. Also, when apredetermined voltage (e.g., 1.6 V) is applied to the corresponding oneof the word lines WL1 to WLkn and a lower voltage (e.g., −2.3 v) isapplied to the corresponding one of the bit lines BL1, BL2, . . . , data“1” is written. In each of the reference memory cells RM, during areference write operation, a predetermined voltage (e.g., 1.6 V) isapplied to all the word lines RWL1 to RWLk and a predetermined voltage(e.g., 1.6 V) is applied to the corresponding one of the bit lines BL1,BL2, . . . , data of which level is between the data “1 ” and data “0”is written. Thus, the memory cell M in which the data “1” is stored hasa low threshold voltage, the memory cell M in which the data “0” isstored has a high threshold voltage, and the reference memory cell RM inwhich the data of the level that is between the data “1” and data “0” isstored has an intermediate threshold voltage.

Also, during a read operation, when a predetermined voltage (e.g., 1.6V) is applied to the corresponding one of the word lines WL11 to WLkn,the amount of current supplied to the corresponding one of the bit linesBL1, BL2, . . . becomes different. The NMOS transistors N7 of theisolation gates IS1 to ISk are turned on in response to correspondingisolation control signals (IE1L1, IE1R1) to (IEk1, IEkR1), respectively.Also, the NMOS transistors N8 of the isolation gates IS1 to ISk areturned on in response to corresponding isolation control signals (IE1L2,IE1R2) to (IEkL2, IEkR2), respectively.

The precharge circuit PRE precharges the corresponding one of pairs ofsense bit lines (SBL1, SBL1B), (SBL2, SBL2B), . . . to a prechargevoltage (VBL) level in response to a precharge control signal VPRE. ThePMOS sense amplifier PSA senses a low-level voltage of one line of thecorresponding one of the pairs of bit lines (BL1, BL1B), (BL2, BL2B), .. . and amplifies the sensed voltage to a voltage (LA) level. The NMOSsense amplifier NSA senses a high-level voltage of one line of thecorresponding one of the pairs of bit lines BL1, BL1B), (BL2, BL2B), . .. and amplifies the sensed voltage to a voltage (LAB) level. Forexample, the voltages LA and LAB are 2.3 V and −2.3 V, respectively,during the write and read operations. In addition, the voltages LA andLAB are 1.6 V and 0 V (or −2.3 V), respectively, during the referencewrite operation. The column selection gates CSG transmit data betweenthe pairs of sense bit lines (SBL1, SBL1B), (SBL2, SBL2B), . . . and thecorresponding one of pairs of data (D1, D1 b), (D12, D12B), . . . , and(DOk, DOkB) in response to the corresponding column selection signaltransmitted through column selection signal lines CSL1 to CSLm.

The row decoder 110 decodes a first row address RA1 in response to anactive command ACT and selects one of the word lines WL11 to WLkn, andsimultaneously selects the reference word lines RWL1 to RWLk in responseto a reference write command RWR. The column decoder 120 decodes acolumn address CA in response to a read command RD or a write commandWRY and selects one of the column selection signal lines CSL1 to CSLm.

The controller 130 receives a second row address RAD along with theactive command ACT, activates isolation control signals ILEOR2, IE1L2, .. . , and IE(k+1)L2 in response to the reference write command RWR inorder to turn on the NMOS transistors N8 of the isolation gates ISO toIS(k+1) disposed on both sides of all the memory cell array blocks BLK0to BLK(k+1), disables the precharge control signal VPRE, and applies thesense amplification voltages LA and LAB, for example, 2.3 V and 1.6 V toall the sense amplifier circuits SA. Also, the controller 130 disablesthe precharge control signal VPRE in response to the write command WRY,activates the corresponding isolation control signals in order to turnon the NMOS transistors N8 of the isolation gates disposed on both sidesof the memory cell array block designated by the second row address RADand also turn on the NMOS transistors N7 of the isolation gates ofadjacent memory cell array blocks on both sides of the designated memorycell array block, and applies the sense amplification voltages LA andLAB, for example, 2.3 V and −2.3 V to the sense amplifier circuits SAdisposed on both sides of the designated memory cell array block.

In addition, the controller 130 disables the precharge control signalVPRE during a first period in response to the read command RD, activatesthe corresponding isolation control signals in order to turn on the NMOStransistors N7 of the isolation gates of the memory cell array blockdesignated by the second row address RAD and turn on the NMOStransistors N8 of the isolation gates of adjacent memory cell arrayblocks on both sides of the designated memory cell array block, appliesthe sense amplification voltages LA and LAB to the sense amplifiercircuits SA disposed on both sides of the designated memory cell arrayblock during a second period, and activates the corresponding isolationcontrol signals in order to turn on the NMOS transistors N8 of theisolation gates disposed on both sides of the designated memory cellarray block during a third period. The controller 130 activates theprecharge control signal VPRE and applies a predetermined prechargevoltage (e.g., 1.2 V or 1.6 V) before and after the reference writeoperation, the write operation, and the read operation.

FIG. 3 is a timing diagram illustrating the reference write operation ofthe semiconductor memory device shown in FIG. 2.

When the reference write command RWR is applied, the row decoder 110activates all reference word line selection signals in order to selectall the reference word lines RWL0 to RWL(k+1). For example, a voltage of1.6 V is applied to the reference word lines RWL0 to RWL(k+1). Thecontroller 130 activates the isolation control signals IE0R2, EI1L2,IE1R2, . . . , and IE(k+1)L2 and applies predetermined levels ofvoltages LA and LAB for enabling the sensing operation of the all thesense amplifier circuits SA. For example, a voltage LA of 2.3 V and avoltage LAB of 0 V or 1.6 V is applied. As a result, the NMOStransistors N8 of the isolation gates IS0 to IS(k+1) are turned on.

The column decoder 120 activates all the column selection signals inorder to select all the column selection signal lines CSL1 to CSLm. As aresult, the NMOS transistors N5 and N6 of all the column selection gatesCSG are turned on. In this case, when a pair of data (i.e., high-leveldata and low-level data) are applied through all pairs of datainput/output lines D1/D1B to Dk/DkB, a voltage difference is generatedbetween all the pairs of sense bit lines (SBL1, SBL1B), (SBL2, SBL2B), .. . . This voltage difference is amplified by the PMOS sense amplifierPSA and the NMOS sense amplifier NSA so that the voltage LA is appliedto all the sense bit lines SBL1, SBL2, . . . and the voltage LAB isapplied to all inverted sense bit lines SBL1B, SBL2B, . . . . Thus, thevoltage LAB is applied also to all the bit lines BL1, BL2, . . . . As aresult, data of which level is between data “1” and data “0” is storedin all the reference memory cells RM, so that all the reference memorycells RM have a threshold voltage that is between the threshold voltageof a memory cell that stores the data “1” and the threshold voltage of amemory cell that stores the data “0.” Thus, the reference memory cellsRM are written in the reference write operation.

FIG. 4 is a timing diagram illustrating the write operation of thesemiconductor memory device shown in FIG. 2 when data “1” and data “0”are each written in the memory cells MC coupled to the word line WL11and bit lines BL1 and BL2 of the memory cell array block BLK1.

When the active command ACT and the first and second addresses RA1 andRAD are applied, the row decoder 110 decodes the first row address RA1and activates the word line WL11. For example, a voltage of 1.6 V isapplied to the word line WL11. The controller 130 decodes the second rowaddress RAD and activates the isolation control signals IE1L2 and IE1R2.Also, when the write command WRY and the column address CA are applied,the column decoder 120 decodes the column address CA and activates thecolumn selection signal line CSL1.

In response to the write command WRY, the controller 130 applies thevoltages LA and LAB for enabling the operation of the sense amplifiercircuits SA disposed on both sides of the memory cell array block BLK1.For example, a voltage LA of 2.3 V and a voltage LAB of −2.3 V areapplied. Then, the column selection gates CSG disposed on both sides ofthe memory cell array block BLK 1 are turned on, and the NMOStransistors N8 of the isolation gates IS1 disposed on both sides of thememory cell array block BLKT are turned on. Thus, pairs of data lines(D1, D1B) and (D12, D12B) are coupled to the corresponding pairs ofsense bit lines (SBL1, SBL1B), (SBL2, SBL2B), and the correspondinginverted sense bit lines SBL1B and SBL2B are coupled to thecorresponding bit lines BL1 and BL2 of the memory cell array block BLK1.Accordingly, the pair of data (low-level data and high-level data) inthe pair of data lines (D1, D1B) are transmitted to the pair of sensebit lines (SBL2, SBL2B), and the pair of data (high-level data andlow-level data) in the pair of data lines (D12, D12B) are transmitted tothe pair of sense bit lines (SBLT, SBL1B).

The voltages of the pairs of sense bit lines (SBLT, SBL1B) and (SBL2,SBL2B) are amplified by the sense amplifiers PSA and NSA. For example,the pair of sense bit lines (SBL1, SBL1B) are amplified to 2.3 and −2.3V, respectively, and the pair of sense bit lines (SBL2, SBL2B) areamplified to -2.3 and 2.3 V, respectively. As a result, data “1” iswritten in the memory cell M coupled to the word line W11 and bit lineBL1 of the memory cell array block BLK1, and data “0” is written in thememory cell M coupled to the word line WLT 1 and bit line BL2. Thus, thememory cells MC are written in the write operation.

FIG. 5 is a timing diagram illustrating the read operation of thesemiconductor memory device shown in FIG. 2 when data “1” and data “0”are each read from the memory cells M coupled to the word line W11 andbit lines BL1 and BL2 of the memory cell array block BLK1.

When the active command ACT and the first and second addresses RA1 andRAD are applied, the row decoder 110 decodes the first row address RA1and activates the word line W11 and the reference word lines RWL0 andRWL2. For example, a voltage of 1.6 V is applied to the word line WL11and the reference word lines RWL0 and RWL2. The controller 130 decodesthe second row address RAD and activates the isolation control signalsIE1L1, IE1R1, IE0R2, and IE2L2.

Specifically, the word line WL11 and the isolation control signalsIE1L1, IE1R1, 1E0R2, and IE2L2 are activated during a period T1. Thus,the NMOS transistors N7 of the isolation gates IS1 disposed on bothsides of the memory cell array block BLK1 and the NMOS transistors N8 ofthe isolation gates IS0 and IS2 disposed on both sides of the memorycell array block BLK1 are turned on. Also, the voltage of the bit lineBL1 of the memory cell array block BLK1 becomes a voltage of VBL-Vth1left after a threshold voltage Vth1 of the memory cell M that storesdata “1” is subtracted from a precharge voltage VBL. The voltage of thebit line BL2 becomes a voltage of VBL-Vth0 left after a thresholdvoltage Vth0 of the memory cell M that stores data “0” is subtractedfrom the precharge voltage VBL. The voltages of the bit lines BL1 andBL2 become the voltages of the sense bit lines SBL1 and SBL2. Each ofthe voltage of the bit line BL1 of the memory cell array block BLK2 andthe voltage of bit line BL2 of the memory cell array block BLK0 becomesa voltage of VBL-Vth(½) left after a threshold voltage Vth(½) of thereference memory cell RM that stores data of which level is intermediatebetween the data “1” and data “0” is subtracted from the prechargevoltage VBL, and the voltages of the bit lines BL1 and BL2 of memorycell array blocks BLK0 and BLK2 become the voltages of the invertedsense bit lines SBL1B and SBL2B.

Since the threshold voltage Vth1 of the memory cell M that stores thedata “1” is lower than the threshold voltage Vth(½) of the referencememory cell RM that stores the reference level between data “1” and data“0,” the voltage of the sense bit line SBL1 is higher than that of theinverted sense bit line SBL1 B. Similarly, the voltage of the sense bitline SBL2 is lower than that of the inverted sense bit line SBL2B sincethe threshold voltage Vth0 of the memory cell M that stores the data “1”is higher than the threshold voltage Vth(½) of the reference memory cellRM. As a result, voltage difference is generated between each of thepairs of sense bit lines (SBL1, SBL1B) and (SBL2, SBL2B) during theperiod T1.

The controller 130 disables the isolation control signals IE1L1, IE1R1,IE0R2, and IE2L2 in response to the read command RD and applies thevoltages LA and LAB for enabling the operation of the sense amplifiercircuits SA disposed on both sides of the memory cell array block BLK1.For example, a voltage LA of 2.3 V and a voltage LAB of −2.3 V areapplied.

Specifically, the isolation control signals IE1L1, IE1R1, IE0R2, andIE2L2 are disabled and the voltages LA and LAB are applied during aperiod T2. Thus, the NMOS transistors N7 of the isolation gates IS1 andthe NMOS transistors N8 of the isolation gates IS0 and IS1 are turnedoff. Also, the PMOS sense amplifier PSA and the NMOS sense amplifierNSA, which are disposed on both sides of the memory cell array blockBLK1, perform the sensing operation so that the pair of sense bit linesSBL1 and SBL1B disposed on the right side of the memory cell array blockBLK1 are supplied with 2.3 and −2.3 V, respectively, and the pair ofsense bit lines SBL2 and SBL2B disposed on the left side thereof aresupplied with −2.3 and 2.3 V, respectively.

During the period T2, the pairs of sense bit lines (SBL1, SBL1B) and(SBL2, SBL2B) perform sensing and amplification operations.

The controller 130 activates the isolation control signals IE1R1 andIE1L1 after the period T2. The column decoder 120 decodes the columnaddress CA applied along with the read command RD and activates thecolumn selection signal line CSL1.

Specifically, the isolation control signals IE1R1 and IE1L1 areactivated and the column selection signal line CSL1 is activated duringa period T3. Then, the NMOS transistors N8 of the isolation gates IS1are turned on. Thus, a voltage of −2.3 V is applied from the invertedsense bit line SBL1B to the bit line BL1, and a voltage of 2.3 V isapplied from the inverted sense bit line SBL12B to the bit line BL2.Accordingly, data “1” is restored in the memory cell M coupled betweenthe word line WL11 and bit line BL1 of the memory cell array block BLK1,and data “0” is restored in the memory cell M coupled between the wordline WL11 and bit line BL2 thereof. Also, the column selection gates CSGare turned on and transmit data from the pairs of sense bit lines (SBL1,SBL1) and (SBL2, SBL2B) to the corresponding pairs of data lines (D1,D1B) and (D12, D12B). That is, data are restored in the memory cells Mand transmitted during the period T3. Thus, data in the memory cells Mare read and restored during the read operation.

Although data “1” and data “0” have been used to describe reading andwriting operations, such data levels are merely descriptive and may beany level during operation. Furthermore, although particular voltagessuch as 2.3V and 1.6V have been described, one skilled in the art willunderstand that such voltages are examples and other voltages may beused.

Further, the controller 130 activates the precharge control signal VPREand applies the precharge voltage VBL in order to precharge the bitlines BL1, BL2, . . . and the pairs of sense bit lines (SBL1, SBL1B),(SBL2, SBL2B), . . . before and after the reference write operation, thewrite operation, and the read operation.

The memory cells M of the semiconductor memory device according may berefreshed in a similar manner as the read operation except that thecolumn selection signals for activating the column selection signallines CSL1 to CSLm are not activated. Also, the reference memory cellsRM of the semiconductor memory device may be refreshed in a similarmanner to the refresh operation of the memory cells M. In other words,the column selection signal lines CSL1 to CSLm for enabling the columnselection gates CSG are inactivated and the same voltage as a voltageapplied for the reference write operation is applied to the senseamplifier circuit SA, so that the reference memory cells RM can performthe refresh operation.

In an embodiment of a semiconductor memory device, the sense amplifiercircuits correspond one-to-one to the bit lines. Accordingly, all thememory cells M can perform the refresh operation by activating the wordline only once. As a result, since the semiconductor memory deviceactivates the word line only once to perform the refresh operation, atime taken for the refresh operation can be shortened.

In addition, as described above, an embodiment of a semiconductor memorydevice has a simplified configuration of a sense amplifier circuit usedfor a data read operation and a reduced time for a refresh operation.

In one embodiment, a semiconductor memory device includes a memory cellarray including a first memory cell array block and a second memory cellarray block, the first memory cell array block including a memory cellhaving a floating body coupled to a word line, a first bit line, and afirst source line, the second memory cell array block including areference memory cell having a floating body coupled to a reference wordline, a second bit line, and a second source line; a first isolationgate portion for transmitting a signal between the first bit line and aninverted sense bit line during a write operation and during a thirdperiod of a read operation and for transmitting a signal between thefirst bit line and a sense bit line during a first period of the readoperation; a second isolation gate portion for transmitting a signalbetween the second bit line and the inverted sense bit line during thefirst period of the read operation; a precharge portion for prechargingthe sense bit line and the inverted sense bit line to a prechargevoltage level during a precharge operation; and a sense amplifier foramplifying voltages of the sense bit line and the inverted sense bitline to first and second sense amplifying voltage levels during thewrite operation and during second and third periods of the readoperation.

The first isolation gate portion may include a first transistor fortransmitting a signal between the first bit line and the sense bit linein response to a first isolation control signal; and a second transistorfor transmitting a signal between the first bit line and the invertedsense bit line in response to a second isolation control signal. Also,the second isolation gate portion may include a third transistor fortransmitting a signal between the second bit line and the inverted sensebit line in response to a third isolation control signal.

The semiconductor memory device may further include a controller foractivating the second isolation control signal and applying a senseamplifying voltage during the write operation, for activating the firstisolation control signal and the third isolation control signal duringthe first period of the read operation, for applying first and secondsense amplifying voltages during the write operation and during thesecond period of the read operation, and for activating the secondisolation control signal and applying the first and second senseamplifying voltages during the third period of the read operation. Thefirst sense amplifying voltage may be a positive first voltage, and thesecond sense amplifying voltage may be a negative second voltage. Thecontroller may activate the third isolation control signal and apply athird sense amplifying voltage, which is different from the first senseamplifying voltage, during the reference write operation. The thirdsense amplifying voltage may have a voltage level between the positivefirst voltage and the negative second voltage. Also, the semiconductormemory device may perform the precharge operation before and after thewrite operation, before the first period of the read operation, andafter the third period of the read operation.

In another embodiment, a semiconductor memory device includes a memorycell array including a first memory cell array block and a second memorycell array block, the first memory cell array block including firstmemory cells and first reference memory cells, each first memory cellhaving a floating body coupled to a first word line, a first bit line,and a first source line, each first reference memory cell having afloating body coupled to a first reference word line, the first bitline, and the first source line, the second memory cell array blockincluding second memory cells and a second reference memory cell, eachsecond memory cell having a floating body coupled to a second word line,a second bit line, and a second source line, the second reference memorycell having a floating body coupled to a second reference word line, thesecond bit line, and the second source line; a first isolation gateportion for transmitting a signal between the first bit line and aninverted sense bit line during a first write operation and during athird period of a first read operation, for transmitting a signalbetween the first bit line and a sense bit line during a first period ofthe first read operation, and for transmitting a signal between thefirst bit line and the inverted sense bit line during a third period ofa second read operation; a second isolation gate portion fortransmitting a signal between the second bit line and the inverted sensebit line during a second write operation and during the third period ofthe second read operation, for transmitting a signal between the secondbit line and the sense bit line during a first period of the second readoperation, and for transmitting a signal between the second bit line andthe inverted sense bit line during the third period of the first readoperation; a precharge portion for precharging the sense bit line andthe inverted sense bit line to a precharge voltage level during aprecharge operation; and a sense amplifier for amplifying voltages ofthe sense bit line and the inverted sense bit line to first and secondsense amplifying voltage levels during the first and second writeoperations and during second and third periods of the first and secondread operations.

The first isolation gate portion may include a first transistor fortransmitting a signal between the first bit line and the sense bit linein response to a first isolation control signal; and a second transistorfor transmitting a signal between the first bit line and the invertedsense bit line in response to a second isolation control signal. Also,the second isolation gate portion may include a third transistor fortransmitting a signal between the second bit line and the sense bit linein response to a third isolation control signal; and a fourth transistorfor transmitting a signal between the second bit line and the invertedsense bit line in response to a fourth isolation control signal.

The semiconductor memory device may further include a controller foractivating the second isolation control signal and applying first andsecond sense amplifying voltages during the first write operation, foractivating the first and fourth isolation control signals during thefirst period of the first read operation, applying the first and secondsense amplifying voltages during the second and third periods of thefirst read operation, and activating the second isolation control signalduring the third period of the first read operation, for activating thefourth isolation control signal and applying the first and second senseamplifying voltages during the second write operation, and foractivating the second and third isolation control signals during thefirst period of the second read operation, applying the first and secondsense amplifying voltages during the second and third periods of thesecond read operation, and activating the fourth isolation controlsignal during the third period of the second read operation. The firstsense amplifying voltage may be a positive first voltage, and the secondsense amplifying voltage may be a negative second voltage. Also, thecontroller may activate the second isolation control signal and apply athird sense amplifying voltage, which is different from one of the firstand second sense amplifying voltages, during a first reference writeoperation, and may activate the fourth isolation control signal andapply the first and third sense amplifying voltages during a secondreference write operation. The third sense amplifying voltage may have avoltage level between the positive first voltage and the negative secondvoltage.

The semiconductor memory device may perform the precharge operationbefore and after the first and second write operations, before the firstperiod of the first and second read operations, and after the thirdperiod of the first and second read operations.

In another embodiment, the semiconductor memory device may furtherinclude a column selection gate portion for transmitting data betweenthe sense bit line and a data input/output line and for transmittingdata between the inverted sense bit line and an inverted datainput/output line.

In another embodiment, the sense amplifier may include a PMOS senseamplifier including a first PMOS transistor and a second PMOS transistorthat are coupled in series between the sense bit line and the invertedsense bit line and sense high-level data of one of the sense bit lineand the inverted sense bit line to amplify the high-level data to thefirst sense amplifying voltage level; and an NMOS sense amplifierincluding a first NMOS transistor and a second NMOS transistor that arecoupled in series between the sense bit line and the inverted sense bitline and sense low-level data of one of the sense bit line and theinverted sense bit line to amplify the low-level data to the secondsense amplifying voltage level. The precharge portion may comprise athird NMOS transistor and a fourth NMOS transistor that are coupled inseries between the sense bit line and the inverted sense bit line andprecharge the sense bit line and the inverted sense bit line to theprecharge voltage level in response to a precharge control signal.

Furthermore, the reference memory cell (or each of the first and secondreference memory cells) may have a threshold voltage that is higher thana threshold voltage of one of the memory cells that stores data “1” andlower than a threshold voltage of one of the memory cells that storesdata “0.”

Another embodiment is a data write/read method for a semiconductormemory device including a memory cell array including a first memorycell array block and a second memory cell array block, the first memorycell array block including a memory cell having a floating body coupledto a word line, a first bit line, and a first source line, the secondmemory cell array block including a reference memory cell having afloating body coupled to a reference word line, a second bit line, and asecond source line to store data of which level is intermediate betweenone of the memory cells that stores data “1” and one of the memory cellsthat stores data “0;” a precharge portion for precharging a sense bitline and an inverted sense bit line to a precharge voltage level; and asense amplifier for amplifying voltages of the sense bit line and theinverted sense bit line to first and second sense amplifying voltagelevels. The method includes: connecting the first bit line to theinverted sense bit line and transmitting the voltage of the invertedsense bit line, which is amplified by the sense amplifier, to the firstbit line during a write operation; and connecting the first bit line tothe sense bit line and connecting the second bit line to the invertedsense bit line to generate a voltage difference between the sense bitline and the inverted sense bit line during a first period of a readoperation, and amplifying the voltages of the sense bit line and theinverted sense bit line to the first and second sense amplifying voltagelevels using the sense amplifier and connecting the inverted sense bitline to the first bit line during second and third periods of the readoperation.

The sense bit line and the inverted sense bit line may be precharged tothe precharge voltage level using the precharge portion before and afterthe write operation, before the first period of the read operation, andafter the third period of the read operation.

During the write operation, data “1” may be written in the memory cellsdue to impact ionization when the word line is activated and theinverted sense bit line is at a positive voltage level, and data “0” maybe written in the memory cells due to forward biasing when the word lineis activated and the inverted sense bit line is at a negative voltagelevel.

The first bit line may be disconnected from the sense bit line and thesecond bit line may be disconnected from the inverted sense bit lineduring the second period of the read operation, and the first bit linemay be coupled to the inverted sense bit line during the third period ofthe read operation.

Embodiments have been disclosed herein and, although specific terms areemployed, they are used and are to be interpreted in a generic anddescriptive sense only and not for purpose of limitation. Accordingly,it will be understood by those of ordinary skill in the art that variouschanges in form and details may be made without departing from thespirit and scope of the present invention as set forth in the followingclaims.

1. A method of operating a semiconductor memory device including memorycells having floating bodies, the method comprising: activating a wordline of a first memory cell array; activating a reference word line of asecond memory cell array; coupling a bit line of the first memory cellarray to a sense bit line of a sense amplifier; coupling a bit line ofthe second memory cell array to an inverted sense bit line of the senseamplifier; and amplifying a difference between the sense bit line andthe inverted sense bit line.
 2. The method of claim 1, furthercomprising: coupling the inverted sense bit line to the bit line of thefirst memory cell array; and coupling the sense bit line and theinverted sense bit line to a data line and an inverted data line.
 3. Themethod of claim 1, further comprising: applying a first sense amplifyingvoltage and a second amplifying voltage to the sense amplifier duringthe amplifying of the difference between the sense bit line and theinverted sense bit line; wherein the first sense amplifying voltage isdifferent from the second amplifying voltage.
 4. The method of claim 3,further comprising: activating a reference word line of a reference wordline of at least one of the first memory cell array and the secondmemory cell array; coupling a bit line of the at least one of the firstmemory cell array and the second memory cell array to an inverted sensebit line of a corresponding sense amplifier; and applying a third senseamplifying voltage to the corresponding sense amplifier; wherein thethird sense amplifying voltage is between the first sense amplifyingvoltage and the second amplifying voltage.
 5. The method of claim 1,further comprising: decoupling the bit line of the first memory cellarray from the sense bit line of a sense amplifier before amplifying thedifference between the sense bit line and the inverted sense bit line;and decoupling the bit line of the second memory cell array from theinverted sense bit line of the sense amplifier before amplifying thedifference between the sense bit line and the inverted sense bit line.6. The method of claim 1, further comprising: applying a first senseamplifying voltage and a second amplifying voltage to the senseamplifier during the amplifying of the difference between the sense bitline and the inverted sense bit line; coupling a data line and aninverted data line to the sense bit line and the inverted sense bitline; and coupling the inverted sense bit line to the bit line of thefirst memory cell array.
 7. The method of claim 1, wherein: coupling thebit line of the first memory cell array to the sense bit line of a senseamplifier further includes coupling each bit line of the first memorycell array to a sense bit line of a corresponding sense amplifier; andfurther comprising for each corresponding sense amplifier: coupling aninverted sense bit line of the sense amplifier to a corresponding bitline of a memory cell array other than the first memory cell array; andcoupling the inverted sense bit line of the sense amplifier to thecorresponding bit line of the first memory cell array.